Instead of using heavy-weight proprietary firmware (such as BIOS or UEFI) present in most computers, coreboot, previously LinuxBIOS, aims to provide the lowest amount of functionality essential for a contemporary 32-bit or 64-bit operating system to be loaded and run.
For this reason, all of the motherboards that support coreboot must also support coreboot. A limited number of hardware platforms and motherboard models are supported by coreboot. For those who don’t want to deal with proprietary blobs, Libreboot is an alternative to coreboot.
It was at the Advanced Computing Laboratory at Los Alamos National Laboratory (LANL) in the winter of 1999 that the coreboot project began, with the objective of developing a BIOS that would start quickly and intelligently manage problems.
The GNU General Public License governs its use and distribution (GPL). In addition to LANL and SiS, motherboard manufacturers MSI, Gigabyte, and Tyan provide coreboot alongside their normal BIOS or give specifications of the hardware interfaces for certain of their motherboards. Coresystems and Linux Networx, Inc. are other major contributors.
Coreboot is made possible in part by Google. In 2009, the CME Group, a group of futures exchanges, started to sponsor the coreboot initiative. Coreboot has been approved for the Google Summer of Code seven years in a row (2007–2014).
The first three Chromebooks are the only ones that don’t use coreboot. Support for ARM processors has been added to Das U-Boot by integrating its code. It was in June of this year that Coreboot started using the NSA program Ghidra for its reverse engineering work on firmware-specific issues, after its open-source release.
Any ELF executable, such as iPXE, gPXE, or Etherboot that can boot over the network, or SeaBIOS that can load a Linux kernel, Microsoft Windows 2000 and later, and BSDs (before, Windows 2000/XP and OpenBSD support was supplied via ADLO, may be loaded by Coreboot.
Myrinet, Quadrics, or SCI cluster interconnects may also be used to load a kernel from Coreboot.
Directly booting other kernels like Plan 9 is also doable. Coreboot may use a boot loader like GNU GRUB 2 that supports coreboot instead of loading the kernel itself.
Coreboot is mostly written in C, with some assembly code thrown in for good measure. As opposed to modern PC BIOS, which is often written in assembly, using C as the major programming language makes code audits simpler. This leads to enhanced security.
Once the hardware has been initialized to the bare minimum by Coreboot, it hands control back to the operating system. When the operating system takes control, coreboot code is no longer executing.
Coreboot has a feature that allows the x86 version to operate in 32-bit mode after only 10 instructions] (almost all other x86 BIOSes run exclusively in 16-bit mode).
In some ways, it resembles the present UEFI firmware found on later models of personal computers (PC). Coreboot is unable to perform BIOS call functions on its own. It is possible to load operating systems like Windows 2000/XP/Vista/7 and BSDs using the SeaBIOS payload, which provides BIOS functions.
BIOS calls are only used during early startup and as a fallback mechanism by most current operating systems, which access hardware in a different way.
Coreboot supports IA-32, x86-64, ARM, ARM64, MIPS, and RISC-V CPU architectures. Starting with the OLPC’s Geode GX CPU, supported SOC platforms include AMD Geode.
Artec Group added Geode LX support for their ThinCan model DBE61; that code was accepted by AMD and further modified for the OLPC once it was updated to the Geode LX platform, and it is further developed by the coreboot community to support additional Geode variations.
Flashrom may be used to flash Coreboot onto a Geode platform. Many AMD CPUs and chipsets are now supported by coreboot after the original development on AMD Geode-based devices.
The 0Fh and 10h (K8 core) families of processors, as well as the more contemporary 14h family, are in the list (Bobcat core, Fusion APU). AMD’s RS690, RS7xx, SB600, and SB8xx chipsets are also supported by Coreboot.
A bootstrap protocol for AMD64 mainboards called AMD Generic Encapsulated Software Architecture (AGESA) was made open source in early 2011 in order to offer the necessary functionality for coreboot system startup on AMD64 hardware.
However, AMD never used these releases as a foundation for further development and eventually stopped supporting them. Coreboot or one of its variations may be preinstalled on a variety of devices. Chromebooks with x86 processors.
Rebranded ThinkPads X200 and T400 (available from Mini free, originally known as Gluglug) as well as ThinCan models DBE61, DBE62, and DBE63, and fanless server/router hardware made by PC Engines are also examples of “rebranded” Post card.
Coreboot TianoCore firmware, which includes open source Embedded Controller firmware, is used on certain System76 PCs. Coreboot is an alternative firmware used by StarLabs Systems.
Developing And Debugging Coreboot
Every chipset and motherboard that coreboot supports must be ported to use coreboot. Coreboot initializes the serial port (address cache and registers only) before initializing RAM so that it may send out debug messages to a terminal connection.
Port 0x80 may also receive byte codes that are shown on a POST card’s two hex-digit display. After a computer has started up, a switch may be flipped to enable it to “flash” or reprogram a second device.
An external EEPROM/NOR flash programmer is an option, although it’s more costly.
In addition, CPU emulators such as the Sage SmartProbe may either replace the CPU or connect through a JTAG interface. BIOS emulators may be used to build or download code rather than flashing the BIOS device.